Recently, various power conversion apparatuses like an inverter and a converter which utilize insulated-gate type power semiconductor devices, such as high-voltage-withstandable IGBT and power MOS-FET, are in development. In general, this type of power conversion apparatus is formed as a power semiconductor module that includes a power semiconductor device and a drive circuit thereof. The drive circuit controls a gate voltage to be applied to a control electrode of the power semiconductor device in accordance with an input signal, thereby turning ON and OFF the power semiconductor device.
In the meantime, when the power semiconductor device is short-circuited in the power semiconductor module, a phenomenon such that the gate voltage oscillates is often observed. More specifically, for example, as illustrated in FIG. 7 that indicates changes in a gate voltage Vge, collector voltage Vce, and collector current Ic when an IGBT turns ON, the gate voltage Vge oscillates in some cases. Note that FIG. 7 indicates an oscillation phenomenon at the time of the short-circuit of an IGBT which is described in the document, Power Electronic Specialist Conference (PESC), 2002, pp. 1758-1763.
This oscillation phenomenon of the gate voltage Vge causes not only Electro-Magnetic Interference (EMI) to other electronic apparatuses due to electromagnetic waves emitted owing to oscillation, but also a gate destruction of the power semiconductor device. Hence, a suppression of the oscillation of the gate voltage Vge is desirable.
The gate voltage oscillation is caused by the presence of a resonant circuit formed by parasitic capacitances, inductances, and wiring resistances, etc., in the power semiconductor module. Hence, according to conventional technologies, for example, a resistance value of the gate resistance is set to be high for damping the resonant circuit, or the Q-value in the resonant circuit is decreased so as to suppress an oscillation.
In contrast, JP 2014-230307 A discloses, when simultaneously and parallelly driving multiple power semiconductor devices, in order to decrease a current unbalance among the power semiconductor devices, the values (resistance values) of the gate resistances of the multiple power semiconductor devices are changed. In particular, JP 2014-230307 A discloses to have a time lag in the timing of changing the resistance value of the gate resistance in accordance with a current flowing through each of the multiple power semiconductor devices.
According to the technology disclosed in JP 2014-230307 A, because of the time lag in the timing of changing the resistance value of the gate resistance in accordance with a current flowing through each of the multiple power semiconductor devices, a time lag can be set in the turn-ON timing of each power semiconductor device and in the turn-OFF timing thereof. Consequently, the current unbalance among the multiple power semiconductor devices can be effectively decreased.
In the meantime, in recent years, there is a tendency such that the Q value of the resonant circuit formed in a power semiconductor module increases in accordance with a reduction of inductance of the packaged power semiconductor module, a reduction of capacity due to fast-speed operation of a power semiconductor device, and further an increase of gain of the power semiconductor device due to an increase of allowed current to flow therethrough. In accordance with such a tendency, the oscillation of the gate voltage Vge observed at the power semiconductor module can increase in comparison with conventional technologies. In order to suppress such an intense oscillation of the gate voltage Vge, a dumping to the resonant circuit by, for example, the gate resistance that has a much greater resistance value will be necessary. When, however, the resistance value of the gate resistance is increased, the switching speed of the power semiconductor device decreases, and further a switching loss increases.
The technology of achieving the variable gate resistance disclosed in JP 2014-230307 A merely has a time lag in the timing of changing the resistance values of the multiple gate resistances in accordance with respective currents flowing through the multiple power semiconductor devices. Hence, this technology does not address the oscillation of the gate voltage due to a short-circuit of the power semiconductor device.
The present disclosure has been made in view of the foregoing circumstances, and an objective is to provide a power semiconductor module and a drive circuit thereof which employ a simple structure that can effectively suppress an oscillation of a gate voltage at the time of a short-circuit of an insulated-gate type power semiconductor device in the power semiconductor module.